I was working on the proposed variant for cheap SiLabs F326. Infostar, how did you measure the CLK freq? 25 MHz from a device clocked at 24 MHz sounds somewhat strange. But it won't contain many enhancements beside the AS mode and better encoded state machine. Zhongyb, I'll make a release soon and announce it here. Anyone reading here who has a spare Xilinx Platform Cable USB, willing to donate it for this development? X-Mas time. Unfortunately, there's absolutely no Xilinx cable anywhere near me now, so I can't try. Either it would have to be reprogrammed each time you swap the firmware, or we need to find out what's inside (at least for simple bit banging). Well, maybe there's still a little problem with the CPLD in the Xilinx cable. :idea: In other words, the usb_jtag firmware (with slight modifications) could be downloaded to a Xilinx Platform Cable USB and effectively make it an Altera USB-Blaster (until next powerdown), compatible with Altera tools like Quartus! Then you could change between support for Xilinx or Altera by just re-enumerating the adapter (swapping the firmware) without unplugging. There's a site describing a FX2 solution for Xilinx it should be possible to adapt the FX2 firmware of my adapter for that device. Are you looking for an adapter that exactly behaves like a Xilinx Platform Cable USB, or just a possibility to program Xilinx devices with my adapter? Regarding Xilinx, I'm not planning any Xilinx support. maybe pullups/downs are required/missing/. Do you have everything wired correctly? nCE, nCS. Regarding the failure at 24 MHz, see my earlier post. The cable between CPLD to target should not exceed 10 cm in length. If you want to attach your cable directly to a device with 3.3V logic you should another CPLD, or, as Altera does it, a level translator/driver between the devices. target JTAG interface.įor example, we once had (with a Cyclone device) 10 kOhm pullups on TDI and TMS and 10 kOhm pulldown on TCK, and experienced some problems, but they were solved after we learned that TCK pulldown should be 1 kOhm.įor the CPLD variant I actually used a EPM7064SLC44-10, because I needed 5V logic interface. Whenever I experienced problems, it was due to wrong connections, bad pullup/pulldown resistors on the target JTAG interface, or mismatch between logic levels (3.3/5 V) of Blaster vs. Try reducing the clock to the CPLD from 24 MHz to, say, 6 MHz. It may still be a critical timing in the logic, but I'm using it even slightly "overclocked" at 25 MHz and haven't had any errors since months. If it works "partially" for you, "sometimes" or "it programs the device, but the device doesn't work afterwards", your setup maybe isn't suitable for clear transmission of signals at several MHz. Please manually integrate the code from my previous postings here (until I find time to make a new "release"). The ZIP on my site doesn't yet contain the updates that make AS mode work. ![]() ![]() I've received some mails from others who used my logic with varying success.
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